Process variation during chip manufacture is recognized as a major source of parametric yield loss. In the future, due to scaling down of complementary metal-oxide semiconductor (CMOS) transistor sizes, the situation is expected to get worse. Process variation causes high variability in gate delays and leakage current, which leads to high variability of chip operational frequency and power consumption. Due to chip-to-chip and within chip (intra-chip) variability, only some manufactured chips satisfy both performance and power requirements. The rest are either too slow or consume too much power. It is these non-compliant chips that represent parametric yield loss.
A number of approaches have been proposed to address this problem. A conservative design approach sets chip timing and power to a stricter target than required. To illustrate this point, ideally there would be no variability and chip timing and power requirements would just come from the specifications on the chip. If, however, due to variability the power varies, e.g., by 25 percent (%), and performance varies, e.g., by 20%, then in order to make all chips operational the chips have to be designed to be 25% faster than is required and consume 20% less power than is required. The main disadvantages of this approach are larger chip area and higher design costs.
Another approach, speed binning, reduces parametric yield loss by accepting low performance chips and selling them at discount price. See, for example, A. Datta et al., “Profit aware circuit design under process variations considering speed binning,” IEEE Trans. on VLSI vol. 16, no. 7, pgs. 806-815 (July 2008). However, application-specific integrated circuit (ASIC) chips often have strict requirements for frequency and power. Chips not satisfying those frequency and power requirements have no value at all. Additionally, selling chips at a discount price reduces profits.
Yet another approach, body biasing, (see, for example, C. Neau et al., “Optimal body bias selection for leakage improvement and process compensation over different technology generations,” ISLPED, pgs. 116-121 (August 2003) and T. Chen et al., “Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation,” IEEE Trans. on VLSI, vol. 11, no. 5, pgs. 888-899 (October 2003) (hereinafter “T. Chen”)) either reduces transistor leakage or improves gate delays. This approach requires connecting transistor bodies to a biasing voltage source. The wiring needed to do this, however, negatively affects chip routability, as well as increases design time and cost and is impractical for silicon-on-insulator (SOI) technology.
Therefore, improved techniques for reducing parametric yield loss would be desirable.